74HC138 3-Line to 8-Line Decoder Demultiplexer IC

The 74HC138  decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). Three enable inputs (E1, E2, and E3) are available on the device. Unless E1 and E2 are LOW and E3 is HIGH, all outputs will be HIGH. With just four ‘138 ICs and one inverter, this multiple enable function enables straightforward parallel expansion to a 1-of-32 (5 to 32 lines) decoder. By using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes, the ‘138 may be utilised as an eight output demultiplexer. Clamp diodes are used as inputs. This allows current limiting resistors to be used to interface inputs to voltages greater than VCC.

The 74HC138 decoder is a memory address decoder or data routing device that uses sophisticated silicon-gate CMOS technology. The circuit has the strong noise immunity and low power consumption that CMOS technology is known for. In addition, it has speeds that are comparable to low-power Schottky TTL logic. There are three binary choose inputs on the 74HC138 (A, B, and C). These inputs decide which of the eight typically HIGH outputs goes LOW if the device is enabled. Meanwhile, there are two active LOW and one active HIGH enables (G1, G2A, and G2B) to make decoder cascading easier. The outputs of the decoder can power up to ten low-power Schottky TTL equivalent loads. And they’re pin and functionally equivalent to the 74LS138. Diodes to VCC and ground prevent all inputs from harm caused by static discharge.