74HC165 high-speed PARALLEL-IN/SERIAL-OUT register designed based on advanced silicon-gate CMOS technology. It offers low power consumption and high noise immunity of standard CMOS integrated circuits, beside the power to drive 10 LS-TTL loads. This 8-bit serial register capable of shifting data from Q0 to Q7 when clocked. Parallel inputs to every stage enabled by a low level at the SHIFT/LOAD input. Also it comes with a gated CLOCK input and a complementary output from the eighth bit. Here Clocking obtained via a 2-input NOR gate allowing one input to used as a CLOCK INHIBIT function.
Meanwhile, holding either of the CLOCK inputs high inhibits clocking. And holding either CLOCK input low with the SHIFT/LOAD input high enables the other CLOCK input. During the positive-going edge of the clock, the data transfer occurs. Whereas the Parallel loading inhibited as long because the SHIFT/LOAD input remains HIGH. When taken LOW, data at the parallel inputs loaded directly into the register independent of the state of the clock. The 74HC logic family function also as pin-out compatible with the standard 74LS logic family. All inputs shielded from damage because of static discharge by internal diode clamps to VCC and ground.
In Parallel In Serial Out (PISO) shift registers, the data loaded onto the register in parallel format while retrieved from it serially. PISO register features a control-lineand combinational circuit (AND and OR gates) additionally to the essential register components (flip-flops) fed with clock and clear pins.