74LS290 4-Bit Binary Counter IC

74LS290 designed as a high-speed 4-bit MOD-10 ripple type counters partitioned into two sections. In which each counter contains four master-slave JK flip-flops. Which internally connected to supply MOD-2 (count to 2) counter and MOD-5 counter. 74LS290 also offers an independent toggle JK flip-flop by CLKA and therefore the other three driven by the CLKB. The section triggered by a HIGH-to-LOW transition on the clock inputs. In 74LS290, each section used separately or tied together (Q to CP)to form BCD, Bi-quinary, or Modulo-10 counters. These counters feature a 2-input gated Master Reset (Clear) and  also has a 2-input gated Master Set (Preset 9).  A separate clock input that initiates state changes of the counter on the HIGH-to-LOW clock transition.

State changes of the Q outputs don’t occur simultaneously due to internal ripple delays. Therefore, decoded output signals fed to decoding spikes and not used for clocks or strobes. The Q0 output of every device meant and specified to drive the rated fan-out plus the CP1 input of the device. A gated AND asynchronous Master set (MS1 ⋅ MS2) provided on both counters that override clocks and the MR inputs and sets the outputs to nine (HLLH). Since the output from the divide-by-two section not internally connected to the upcoming stages, the devices also operated in various counting modes.

• BCD Decade (8421) Counter — In this mode, output CP1 must be externally connected to input Q0. The CP0 input receives the incoming count and a BCD count sequence generated.
•  Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 output must be externally connected to the CP0 input. The input count is then fed to the CP1 input. And a divide-by-ten square wave received at output Q0.
• Divide-By-Two and Divide-By-Five Counter — No external interconnections required. the primary flip-flop employed as a binary element for the divide-by-two function (CP0 because the input and Q0 because the output). The CP1 input employed to get binary divide-by-five operation at the Q3 output.