74LS293 4-Bit Binary Counter IC

74LS293 designed as a high-speed 4-bit MOD-16 ripple type counters partitioned into two sections. In which each counter contains four master-slave JK flip-flops. Which internally connected to supply MOD-2 (count to 2) counter and MOD-8 counter. 74LS293 also offers an independent toggle JK flip-flop by CLKA and therefore the other three driven by the CLKB. The section triggered by a HIGH-to-LOW transition on the clock inputs. In 74LS293, each section used separately or tied together (Q to CP)to form BCD, Bi-quinary, or Modulo-16 counters. Both of the counters feature a 2-input gated Master Reset (Clear).  And a separate clock input that initiates state changes of the counter on the HIGH-to-LOW clock transition.

State changes of the Q outputs don’t occur simultaneously due to internal ripple delays. Therefore, decoded output signals fed to decoding spikes and not used for clocks or strobes. The Q0 output of every device meant and specified to drive the rated fan-out plus the CP1 input of the device. A gated AND asynchronous Master Reset (MR1 ⋅ MR2) provided on both counters that override clocks and resets (clears) all the flip-flops. Since the output from the divide-by-two section is not internally connected to the upcoming stages, the devices could also be operated in various counting modes.

• 4-Bit Ripple Counter — In this mode, output Q0 must be externally connected to input CP1. The input count pulses fed to input CP0. Simultaneous division of two , 4, 8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs
• 3-Bit Ripple Counter — The input count pulses given to input CP1. Simultaneous frequency divisions of two , 4, and eight are performed at the Q1, Q2, and Q3 outputs. Also Independent use of the primary flip-flop out there if the reset function coincides with reset of the 3-bit ripple-through counter.