74LS73 Dual Positive Pulse Triggered J-K Flip-Flop IC

The 74LS73 designed as a dual in-line positive pulse triggered JK flip flop IC. It’s made up of two J-K flip-flops, each with its own J-K, clock, and direct clear inputs. After a complete clock pulse, the flip-flops process the J and K data. The slave is segregated from the master when the clock is low. The data from the J and K inputs is sent to the master on the clock’s positive transition. The J and K inputs are disabled when the clock is high.

The data from the master is sent to the slave on the clock’s negative transition. While the clock is high, the logic states of the J and K inputs must not change. On the falling edge of the clock pulse, data is transferred to the outputs. Regardless of the logic values of the other inputs, a low logic level on the clear input will reset the outputs. This IC can also be utilised as a small programmable memory or in latching applications. The 74LS73 is designed to work in temperatures ranging from 0° C to 70° C.

The JK Flip Flop designed as a gated RS flip flop with the addition of the clock input circuitry. When both the inputs S and R are adequate to logic “1”, the invalid condition takes place. Thus to stop this invalid condition, a clock circuit is introduced. The JK Flip Flop has four possible input combinations due to the addition of the clocked input. The four inputs are “logic 1”, ‘logic 0”. “No change’ and “Toggle”.

Applications

• PCs and notebooks
• Digital Electronics
• Network equipment
• Shift Registers
• Memory/Control Registers
• EEPROM circuits
• Latching devices