74LS112 Dual J-K Negative Edge Triggered Flip-Flop IC

74LS112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to every flip-flop. It comprises of two independent negative-edge-triggered J-K flip-flops with individual J-K, clock, and direct clear inputs. The 74LS112 IC features a wide selection of working voltage, a good range of working conditions, and directly interfaces with CMOS, NMOS, and TTL. Moreover, output of IC always comes in TTL which makes it easy to figure with other TTL devices and microcontrollers.

Meanwhile, the J and K data is processed by the flip-flop on the falling fringe of the clock pulse. The clock triggering occurs at a voltage level and isn’t directly associated with the transition time of the falling edge of the clock pulse. Data on the J and K inputs could also be changed while the clock is HIGH or LOW without affecting the outputs as long because the setup and hold times are not violated. Meanwhile, a low logic level on the preset or clear inputs will set or reset the outputs no matter the logic levels of the opposite inputs.

The JK Flip Flop designed as a gated RS flip flop with the addition of the clock input circuitry. When both the inputs S and R are capable logic “1”, the invalid condition takes place. In order to prevent this invalid condition, a clock circuit is introduced. Moreover, the JK Flip Flop comprises of four possible input combinations thanks to the addition of the clocked input. The four inputs are “logic 1”, ‘logic 0”. “No change’ and “Toggle”.

Applications

• PCs and notebooks
• Digital Electronics
• Shift Registers