74LS166 Parallel Load 8-Bit Shift Register IC
74LS166 Parallel Load 8-Bit Shift Register IC Original price was: ₹23.00.Current price is: ₹15.00. inc. GST
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74LS195 Universal 4-Bit Shift Register IC
74LS195 Universal 4-Bit Shift Register IC Original price was: ₹38.00.Current price is: ₹25.00. inc. GST

74LS194 4-Bit Bidirectional Universal Shift Register IC

Original price was: ₹53.00.Current price is: ₹35.00. inc. GST

  • 4-Bit Bidirectional Universal Shift Register
  • High-level input voltage: 2V
  • Low-level input voltage: 0.8V
  • High-level output current: -0.4mA
  • Low-level output current: 8mA
  • Input clamp voltage: -1.5V
  • Maximum clock frequency: 25MHz
  • Propagation delay time max: 38ns
  • Supply voltage range: 4.75 to 5.25V
  • Package: DIP-16
Description

The 74LS194A designed as a high Speed 4-Bit Bidirectional Universal register. This IC is widely used in a range of applications as a high-speed multipurpose sequential building block. The 74LS194 bidirectional register was created with nearly all of the features that a system builder needed in a shift register. Parallel inputs and outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and an immediate overriding clear line are all included. It achieves high speeds through a Schottky diode clamped method and is fully compatible with all TTL families. The register can be used in four different ways:

  • Parallel (broadside) load
  • Shift right
  • Shift left
  • Inhibit clock (do nothing)

Furthermore, synchronised parallel loading is achieved by driving both mode control inputs, S0 and S1, HIGH and applying four bits of data. The data is fed into the associated flip-flops and appears at the outputs once the clock input makes a positive transition. During loading, serial data flow is slowed. When S0 remained HIGH and S1 remained LOW, shift right was done synchronously at the rising edge of the clock pulse. In this mode, the shift-right data input is used for serial data. When S0 is LOW and S1 is HIGH, data moves to the left simultaneously. As a result, new data is fed into the serial shift-left input. The clocking of the flip-flop is deactivated when both mode control inputs are set to LOW.

 

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