74LS196 Presettable Decade Counter IC

74LS196 designed as an asynchronously presettable decade and binary ripple counters. In thi high-speed 4-bit MOD-10 ripple type counters partitioned into two sections. In which divide-by-two and divide-by-five sections combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50% duty cycle output. 74LS196 designed based on the Low Power Schottky technology used to achieve typical count rates of 70 MHz and power dissipation of only 80 mW.

In the counting modes,a separate clock input that initiates state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Q outputs don’t occur simultaneously due to internal ripple delays. Therefore, decoded output signals fed to decoding spikes and not used for clocks or strobes.  When utilising external logic to decode the Q outputs, keep in mind that the unequal delays can cause decoding spikes, hence a decoded signal should never be utilised as a clock or strobe. In both circuit types, the CP0 input serves the Q0 flip-flop, whereas the CP1 input serves the divide-by-five. The Q0 output is designed to power the rated fan-out as well as the CP1 input.

This decade counter has a Master Reset (MR) input that overrides all other inputs and forces all outputs to be LOW asynchronously. The data on the Parallel Data inputs (Pn) is asynchronously loaded into the flip-flops by a Parallel Load input (PL), which overrides timed operations. The circuits can be used as programmable counters thanks to this preset functionality. When PL is LOW, the circuits also function as 4-bit latches, loading data from the Parallel Data inputs. PL is also HIGH while the data is being stored.