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CD4027 Dual J-K Master Slave Flip-Flop IC
Original price was: ₹30.00.₹20.00Current price is: ₹20.00. inc. GST
74LS374 Edge-Triggered D Flip-Flop IC
Original price was: ₹23.00.₹18.00Current price is: ₹18.00. inc. GST
74LS373 Octal D-Type Transparent Latch IC
Original price was: ₹25.00.₹15.00Current price is: ₹15.00. inc. GST
- Octal D-Type Transparent Latch
- High-level input voltage:Â 2V
- Low-level input voltage:Â 0.8V
- High-level output voltage:Â 5.5V
- High-level output current:Â -6.5mA
- Input clamp voltage:Â -1.2V
- Propagation delay time:Â 18ns
- Supply voltage range:Â 4.75 to 5.25V
- Package:Â DIP-20
- Eight Latches in a Single Package
- 3-State Outputs for Bus Interfacing
- Hysteresis on Latch Enable
- Edge-Triggered D-Type Inputs
- Buffered Positive Edge-Triggered Clock
- Hysteresis on Clock Input to Improve Noise Margin
- Input Clamp Diodes Limit High-Speed Termination Effects
Description
The 74LS373 is a low-power, high-speed Octal D-type Flip-Flop with independent D-type inputs for each flip-flop and three-state outputs for bus-oriented applications. All flip-flops in the IC receive a buffered Clock (CP) and Output Enable (OE). The flip-flops look transparent to the data when Latch Enable (LE) is HIGH (data changes asynchronously). When LE is set to LOW, the data that matches the setup times locks. When the Output Enable (OE) is LOW, the Data also displays on the bus. The bus output is in a high impedance state when OE is HIGH.
The 74LS373 is a high-speed, low-power Octal D-type Flip-Flop with individual D-type inputs and 3-state outputs for bus-oriented applications. All flip-flops in the IC have a buffered Clock (CP) and Output Enable (OE). The flip-flops are transparent to the data when Latch Enable (LE) is HIGH (data changes asynchronously). When LE is LOW, the data that meets the setup times locks. Also, when the Output Enable (OE) is LOW, the Data shows on the bus. The bus output is in the high impedance state when OE is HIGH.
A D-type latch/flip-flop with two stable states that is designed as a timed latch. A D-type latch has a one-clock-cycle delay in its input. Delay circuits are frequently produced by cascading multiple D-type flip-flops. This was then used in a variety of applications, such as digital television systems. A D flip-flop, sometimes known as a delay flip-flop, is a D-type flip-flop.
Applications
- Used for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers in modern computing systems
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