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CD4085BE CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate IC
Original price was: ₹22.00.₹15.00Current price is: ₹15.00. inc. GST
74HC138 3-Line to 8-Line Decoder Demultiplexer IC
Original price was: ₹45.00.₹35.00Current price is: ₹35.00. inc. GST
CD4086 CMOS Expandable 4 Wide 2 Input AND OR INVERT Gate IC
Original price was: ₹22.00.₹15.00Current price is: ₹15.00. inc. GST
- CMOS Expandable 4 Wide 2 Input AND OR INVERT Gate
- Supply Voltage Range: 3 to 18V
- Input Current: ±10mA
- Power Dissipation: 500mW
- Quiescent Current Max.: 20µA
- Low level Output Voltage Max.: 0.05V
- High level Output Voltage Min.: 4.95V
- Low-level Input Voltage Max.: 1.5V
- High-level Input Voltage Min.: 3.5V
- Propagation Delay Time Max.: 620ns
- Package: DIP-14
Description
CD4086 designed with one 4 Wide 2 Input AND OR INVERT Gate IC with one INHIBIT/EXP’ and an ENABLE /EXP input. For a 4 -wide AOI function INHIBIT/EXP’ connected to Vss and ENABLE /EXP to VDD. It helps to achieve a wide power supply operating range, low power consumption, and high noise margin. This device contains two independent combinations of gates each of which performs the logic AND-OR-INVERT function. The IC also comes as smaller in size and offers much faster speed. Thus makes it highly reliable in every kind of device.
CD4086 Operates at a supply voltage of range between 3V to 18V. This IC designed for operation over the full military temperature range of -55°C to 125°C.All inputs come with protection circuits against static discharge and transient excess voltage. The CD4085BE manufactured in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes). Moreover, it offers a power dissipation at a range of 500mW.
AND-OR-Invert (AOI) logic and AOI gates designed as two-level compound (or complex) logic functions made up of the combination of 1 or more AND gates followed by a NOR gate. The construction of AOI cells is especially efficient using CMOS technology. Where the entire number of transistor gates are often compared to an equivalent construction using NAND logic or NOR logic. The complement of AOI Logic is OR-AND-Invert (OAI) logic where the OR gates precede a NAND circuit.
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