A counter is a sequential circuit that counts pulses in digital logic and computing. The main use of FFs is as a set of counters, which also include an applied CLK signal. These are intended to be used separately as integrated circuits (ICs) in bigger integrated circuits as well as frequently in digital circuits.
There are various sorts of counters, including Johnson counters, asynchronous or ripple counters, synchronous counters, decade counters, ring counters, and up/down counters. In this article, one form of counter, the Up/Down counter-theory, is discussed as it relates to applications.
What is an Up/Down Counter?
The bidirectional counter, often known as an up/down counter, can count in either direction depending on the state of the input control pin. Depending on the application, some of these count up from zero to alter the output state when a fixed value is reached, while others count down from a fixed value to zero to change the output condition. Some counters, such as the TTL 74LS190 and 75LS191, can operate in either an up or down count mode depending on the state of an input pin.
Up/Down Counter Circuit
The 3-bit up/down counter’s circuit diagram is displayed below. Flip-flops were used in the creation of this circuit. Every flip-flop in an up counter is triggered through the normal o/p of the preceding FF (from the primary flip-“Q” flop’s o/p to the next FF’s CLK), whereas every flip-flop in a down counter is activated through the complement o/p of the preceding FF (from the output of first FF to CLK of next FF).
Up/Down Counter Working
The up-down control input can be used to regulate the up/down counteraction. There are two operating modes for this up/down counter: count up and count down. Below are examples of the count-up and countdown tabular forms.
The count-up mode tabular form is shown below.
The count-down mode tabular form is shown below.
As we know, the preceding flip-flop occasionally requires input from the Q output of the primary flip-flop to the CLK of the next flip-flop in up-counting and occasionally from the Q output of the primary FF to the CLK of the next FF for down-counting. A FF can typically hold one bit, hence three FFs are required for a three-bit operation.
To ensure that the count-up and count-down cannot both be in the HIGH condition at the same time, an inverter is placed between the two control lines in the circuit shown above.
The bottom side AND gates will be disabled once the count-up or countdown line is maintained HIGH, resulting in their o/p being zero. They won’t alter the outputs of the OR gate as a result. The higher AND gates will simultaneously turn on. As a result, “QA” will provide the CLK input of the B flip flop as well as the OR gate. Similarly, “QB” will be gated into the C FF’s CLK input. As a result, after applying the input signals, it will start counting up and using the standard binary counting sequence from 000 to 111.
Similar to how upper side AND gates are disabled & lower side AND gates are enabled by permitting both the Q′A & Q′B to flow throughout the CLK inputs of the FFs whenever the count-up or countdown line is held LOW. As a result, when the i/p pulses are applied in this state, the counter will begin counting in the downward direction.
How does the Up/Down Counter Count a Clock Pulse?
Unlike a down counter, which counts from high to low, an up counter counts from low to high. An asynchronous 3-bit up/down counter gets its outputs from FFs complement outputs like Q′ rather than from the flip-flops’ regular o/ps. The initial series of counts is QA QB QC = 111. The status of the CLK “QA” is toggled by each negative edge. Similar to how the QB’ output toggles with every negative transition of the QA’ output, the QC output does the same. As a result, through each clock pulse, the count series continues to decrease from 7 to 0 and so on.
Every flip-flop in an up counter is activated using the complement o/p of the previous FF (from the output of the first FF’s QA to the CLK of the next FF), whereas every flip-flop in a down counter is activated using the normal o/p of the previous FF (from the primary flip-‘QA’ flop’s o/p to the next FF’s CLK).
The initial flip flop in the up counter is wired to logic 0, thus it will toggle on every falling edge.
- When QA = 1 and a falling clock edge occur, the status of the second flip flop, which has its input connected to the first flip flop’s “QA,” changes.
- Similar to the second flip flop, the third flip flop is tied to the second FF’s “QB” and changes states whenever QB = 1 and a falling clock edge occurs. This allows us to create the counting states of a counter. After the eighth falling edge, the counter will once more reach the condition of 0 0 0.
- The first flip flop in the down counter is connected to logic 1, and it toggles on and off for each falling edge.
- When QB’= 1 and a falling clock edge occurs, the second flip flop, whose input is connected to the first FF’s QA’, will change its condition.
- A falling edge of the clock and QB’=1 will cause the third FF, which is also connected to the second FFs QB’, to change its state. This allows us to quickly construct the counting states of a counter. After every eighth falling edge, the counter once more reaches the position of 0 0 0.
Up/Down Counter IC
The Up/Down counter IC, which is also known as the 74193 IC, is a synchronous, 4-bit, MODULO-16 binary counter. The two CLK input pins on this IC are utilised to increment and decrement the fixed value, making the o/p synchronous via the CLK inputs.
IC 74193 Up Down Counter
To create a higher counter or cascade this up/down counter IC, separate Count Up & Count Down terminals are used. A low parallel active load i/p pin is used to start counting through any number, and the master reset pin is used to reset the entire chip.
IC 74193 Pin Configuration
The IC 74193 includes 16-pins where each pin and its function are discussed below.
IC 74193 Pin Configuration
- Pin1 (CLR): This is an active-low clear i/p.
- Pin2 (CLK): This is a clock i/p signal.
- Pin3 (A (LSB), Pin4(B), Pin5 (C) & Pin6 (D(MSB): These pins are preset i/ps to load data.
- Pin7 (ENP): This is an active-high i/p ENP.
- Pin8 (GND): This is a Ground pin.
- Pin9 (Load): This is an active-low load i/p pin.
- Pin10 (ENT): This is an active-high ENT i/p pin.
- Pin11(Qd(MSB)), Pin12(Qc), Pin13 (Qb) & Pin14 (Qa(LSB)): These pins are outputs of Flip-Flops.
- Pin15 (RCO): This is a ripple carry o/p logic from 0 – 1).
- Pin16 (Vcc): This is the power i/p pin.
The features of IC 74193 include the following.
- Its CLK frequency is 32MHz.
- Its power dissipation is 93mW.
- 4-Bit Modulo-16 Up/Down counter.
- Preset i/ps are obtainable.
- It is programmable synchronously.
- Internal ripple carries for quick counting.
- Carry o/p for n bit cascading.
- The propagation time is 14ns.
Up/Down Counter using IC 74193
The IC74193-based up/down counter is displayed below. The circuit is wired in accordance with the diagram that follows. The transparent pins are grounded in the circuit, while pin 16 is connected to the Vcc. The circuits’ inputs are provided by pins 15, 10, 1, and 9. (PA, PB, PC, PD). The outputs are pins 3, 2, 6, and 7. (QA, QB, QC, QD). The inverter’s input pin is connected to pin 12 (carry), while its output pin is attached to pin 11, which is the IC’s load.
Up Down Counter using IC 74193
Pins 5 and 4 are connected to the clocks, up and down, respectively, in the circuit schematic. The up/down counter will start counting in the down direction as soon as pin 4 is raised. This counter count is in an up mode when pin number five is made high. The 74193 IC is therefore employed as a MOD Up/Down N counter.
Difference between Up and Down Counter
The following are some of the ways that the up and down counters differ.
|Up Counter||Down Counter|
|Up counter counts from ‘0’ to the highest number of counts.||Down counter counts from the highest value to the ‘0’ value.|
|It counts events in increasing order.||It counts events in decreasing order.|
Advantages and Disadvantages
An up/down counter has the following advantages.
- The high-speed option allows for cascading of the up/down counter.
- The CLK transition from low to high can be used to concurrently increment or decrement this counter.
- Flip-flops make it relatively simple to design these counters.
The following are some drawbacks of an up/down counter.
- Because they are imprecise at high clock speeds, these counters are not commonly utilized.
- There has to be an additional FF for re-synchronization.
- Due to propagation delay, counting mistakes may occur for high CLK frequencies.
- When counting a large number of bits, these counters have a relatively substantial propagation latency.
- Utilized as a self-reversing counter.
- Used as a clock divider circuit.
- Used in car parking slots.
- These counters are used for low noise emission and low power applications.
- Used as frequency dividers.
- Used in designing an asynchronous decade counter.