74LS160N Synchronous Presettable BCD Decade Counter IC

74LS160N designed as a high-speed 4-bit synchronous counter. 74LS160N is an edge-triggered, synchronously presettable, and cascadable MSI building block. This 74LS160N IC comes as count modulo 10 (BCD) used explicitly for counting, memory addressing, frequency division and other applications. The 74LS160N come with an asynchronous Master Reset (Clear) input that overrides, and independent of,clock and all other control inputs.

The 74LS160N feature a 4-bit synchronous counter with a synchronous Parallel Enable (Load) functin. The counters contains four edge-triggered D flip-flops with the acceptable data routing networks feeding the D inputs. All changes of the Q outputs occur as a result of, and synchronous with, the LOW to HIGH transition of the Clock input (CP). As long as the set-up time requirements are met, there are not any special timing or activity constraints on any of the mode control or data inputs. The mode of operation selected via three control inputs. That is Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET). The Count Mode enabled when the CEP, CET, and PE inputs remain HIGH.

When the PE is LOW, the counters synchronously load the data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock. Either the CEP or CET accustomed to inhibit the count sequence. With the PE held HIGH, a low on either the CEP or CET inputs a minimum of one set-up time before the LOW to HIGH clock transition that cause the prevailing output states to retained. The AND function of the 2 Count Enable inputs (CET • CEP) allows synchronous Cascading without external gating. And at once accumulation over any practical number of bits or digits