CD4026 CMOS Decade Counter with Decoded 7-Segment Display Outputs

CD4026 contains a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage during a numerical display. These devices are particularly advantageous in display applications where low power dissipation and /or low package count are important. Inputs common to both types are CLOCK, RESET, & CLOCK INHIBIT; common outputs are perform and therefore the seven decoded outputs (a, b, c, d, e, f, g). Additional inputs and outputs for the CD4026 include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED “C-SEGMENT” outputs.

A high RESET signal resets the previous decade counter to zero. If the CLOCK INHIBIT signal is low, the counter advances one count at the positive clock signal transition. When the CLOCK INHIBIT signal is high, counter advancement through the clock line is disabled. If the clock line is held high, the CLOCK INHIBIT signal is frequently utilized as a negative-edge clock. The JOHNSON counter has antilock gating, which ensures appropriate counting sequence. During a multi-decade counting chain, the CARRY-OUT (Cout) signal completes one cycle per ten CLOCK INPUT cycles and is used to immediately clock the next decade. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the right segments during a seven segment display device used for representing the decimal numbers 0 to 9. The CD4026 outputs go high only the DISPLAY ENABLE IN is high.

The CD4026 series type supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

APPLICATIONS:

• Decade Counting 7-segment decimal display
• Frequency division 7-segment decimal displays
• Clocks, watches, timers
• Counter/display driver for meter applications