NE564 Phase Locked Loop IC

The NE564 designed as a versatile, high guaranteed frequency phase-locked loop designed for operation up to 50MHz. NE564 consists of a VCO, limiter, phase comparator, and post-detection processor. The NE564 function as a monolithic phase-locked loop with a post-detection processor. The use of Schottky clamped transistors and optimized device geometries extend the frequency of operation to greater than 50MHz. In addition to the classical PLL applications, the NE564 used as a modulator with a controllable frequency deviation.

This NE564 operates with single 5V supply TTL-compatible inputs and outputs Guaranteed operation to 50MHz. Moreover, the  External loop gain control Reduced carrier feedthrough. Hence does not elaborate filtering needed in FSK applications. Meanwhile, this NE 564 used as a modulator Variable loop gain (externally controlled). Also High-speed modems FSK receivers and transmitters Frequency Synthesizers. This PLL manufactured in 16-Pin Plastic Small-Outline (SO) Package, 16-Pin Plastic Dual In-Line Package (DIP), and 16-Pin Plastic Dual In-Line Package (DIP).

The phase-locked loop (PLL) is one of the prominent and commonly used technology in the communication field. With the development of electronic technology toward digitalization, the phase-locked processing of signal must be realized in digital way. Therefore, more and more attentions are paid to the research and application of all digital phase-locked loops. This paper is an introduction about the essential background of PLL, the essential characteristics and structure of PLL, and therefore the basic principles of modulation and demodulation. It provides a concise application about the essential principle and main design process of modulation and demodulation of FSK signal, which are realized by using phase-locked loop chip NE564