74LS161 4-Bit Binary Counter IC

74LS161 4-Bit Binary Counter IC circuit designed as a synchronous reversible up-down counter.  These synchronous, presettable counters provide an internal carry look-ahead feature for application in high-speed counting designs.  The carry output decoded via a NOR gate. Thus preventing spikes during the normal counting mode of operation 74LS161 comes with a 4-bit binary counter in which Synchronous operation provided by all flip-flops clocked simultaneously. As a result,  the outputs change simultaneously as instructed by the count-enable inputs and internal gating.This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.  A buffered clock input triggers the four flip-flops on the rising (positive-going) fringe of the clock input waveform.

This counter made fully programmable that the outputs also preset to either level by placing a low or high.   The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter. And causes the outputs to agree with the data inputs after the next clock pulse. This performed regardless of the levels of the enable input. The clock down up and load inputs buffered to lower the drive requirement.  This significantly reduces the amount of clock drivers etc required for long parallel words.

The clear function for the DM74LS161 is synchronous. And a low level at the clear input sets all four of the flip-flop outputs LOW,  no matter the level of clock, load, or enable inputs. This synchronous clear allows the count length to  modified easily, as decoding the maximum count desired often accomplished with one external NAND circuit. The gate output connected to the clear input to synchronously clear the counter to all or any low outputs.