74LS253 data selector/multiplexer contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. For each of the two 4-line portions, separate output-control inputs are supplied. The 3-state outputs can connect to data lines in bus-organized systems and drive them. The low impedance of the sole enabled output forces the bus line to a high or low logic level when all but one of the common outputs are disabled (in the high-impedance state). There is an output-enable (OE) input for each output. When the outputs’ respective OE is high, they are disabled.
Each of these Schottky-clamped data selectors/multiplexers has inverters and drivers that provide completely complementary binary decoding data selection to the AND-OR gates on-chip. Each of the two four-line portions has its own set of output control inputs. The 3-STATE outputs can connect directly to bus-organized systems’ data lines. The low impedance of the single enabled output will drive the bus line to a HIGH or LOW logic level if all but one of the common outputs are disabled (at a high impedance state).
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