CD4044 designed quad cross-coupled 3-STATE CMOS NAND latches. That mean it comes with four R-S latches, made by using the CMOS NAND logical gate. There exist a common 3-STATE ENABLE input for all four latches. Each latch in the IC consists of a separate Q output and individual SET and RESET inputs. The Q outputs controlled via a common ENABLE input. A logic “1” or high on the ENABLE input connects the latch states to the Q outputs. And also a logic “0” or low on the ENABLE input disconnects the latch states from the Q outputs. This results in an open circuit feature that allow common busing of the outputs. Meanwhile, this IC has many features such as high noise immunity, ESD barring, and excellent thermal overload protection. Meanwhile, CD4044 operates at a DC Supply Voltage Range, (VDD) f -0.5V to +18V.
An SR latch, also known as an SR Flip-Flop, is a logic circuit with two inputs (S and R) and two outputs (Q and Q’). The status of output Q determines the state of this latch. When Q is 1 (High), the latch is said to be SET, and when Q is 0 (Low), the latch is said to be RESET. Two cross-coupled NAND gates or two cross-coupled NOR gates are used to create an SR latch or flip flop.
Application
- Multiple bus storage
- Strobed register
- Four bits of independent storage with output enable
- General digital logic
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