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MC1496PG Balanced Modulator Demodulator IC
₹53.00 Original price was: ₹53.00.₹48.00Current price is: ₹48.00. inc. GST
- Balanced Modulator/Demodulator
- Differential Input Signal:Â 5V
- Maximum Bias Current:Â 10mA
- Carrier Suppression:Â 65dB
- Input Bias Current Max: 30µA
- Input Offset Current Max: 7µA
- Output Offset Current Max: 80µA
- Power Dissipation:Â 33mW
- Package:Â DIP-14
The MC1496PG Balanced Modulator Demodulator IC is designed for applications where the output voltage is the result of a combination of an input voltage (signal) and a switching function (carrier). It may be used for suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, and chopper applications, among other things. An upper quad differential amplifier is powered by a normal differential amplifier with twin current sources in this design. The output collectors are cross coupled, allowing for full wave balanced multiplication of the two input voltages. That is, the output signal is the product of the two input signs multiplied by a constant.
For the carrier and signal voltage levels provided, carrier suppression is defined as the ratio of each sideband output to carrier output. It is very reliant on the carrier input level. Low carrier values don’t fully switch the upper switching devices, resulting in reduced signal gain and, as a result, lesser carrier suppression. A higher than optimal carrier level causes unnecessary device and circuit carrier feedthrough, causing the suppression figure to degenerate once again. A 60 mVrms sinewave carrier input signal was used to characterize the MC1496. This level is often chosen for balanced modulator applications because it gives the best carrier suppression at carrier frequencies around 500 kHz.
The MC1496 requires three externally controlled dc bias voltage values. Maintaining at least 2.0 V collector base bias on all transistors while not exceeding the voltages shown in the absolute maximum rating table are guidelines for setting up these three levels.
- 30 Vdc >= [(V6, V12) − (V8, V10)] >=2 Vdc
- 30 Vdc >= [(V8, V10) − (V1, V4)] >=2.7 Vdc
- 30 Vdc >= [(V1, V4) − (V5)] >=2.7

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